As an industry, we are slowly moving into an era where how we encapsulate small pieces of silicon together is as important as silicon itself. New ways to connect all the silicon include side-by-side, stacked on top of each other, and all sorts of fancy connections that preserve the strengths of chip designs while taking full advantage of them. Today, AMD showed off its next package upgrade: stacking L3 cache on Zen 3 chips, boosting each chip from 32 MiB to 96 MiB, but this time the announcement is for its large EPYC enterprise processors.
AMD's current offering in this market is its third-generation EPYC 7003 processor line, also known as Milan, which offers up to 64 Zen 3 cores covering eight TSMC 7-nanometer chips packaged in combination with GlobalFoundries 14-nanometer Central IO chips.IO chips offer eight DDR4-3200 memory channels and 128-channel PCIe 4.0, among other things, such as security. Today's announcement, or acknowledgment, is that AMD will launch Milan-X in the first quarter.
Milan-x is an upgraded version of Milano with layered L3 cache encapsulation technology. Milan today's 64-core version, with eight 8-core chips, has a total of 256 L3 caches – the Milan-X version will use the added L3 caches on each chip, creating a processor with a total of 768 L3 caches, which is unmatched in the industry. This additional L3 cache builds on TSMC N7's cache density optimized version, which is 36 mm2 in size and adds 64 miBs to the original 32 MIBs.The rest of the chip has spacers around it to help with heat transfer.
Given AMD's disclosure of its stacked cache technology back in June at Computex, we've been expecting consumers and enterprises to mutate to come to market in some way — AMD has promised to come to Zen 3 and put it into production by the end of 2021, and today's announcement confirms the timetable.No announcement has been made as to when it will appear on the consumer product line. That said, today's announcement was short on clear details.
AMD confirmed that the Milan-X will be compatible with current Milan-processors (known as SP3 sockets), but did not list any details about power, frequency, or price. We expect the L3 cache to consume some extra power, so if we work to the limit of 280 W, this means there is some small frequency loss. On top of that, if AMD is constrained by TSMC's wafers and wants to keep the same cost per wafer area, using effective +45% 7nm silicon per chip (36mm2 for top cache, 80.7mm2 for a bottom core chip) should theoretically add +45% to the price. The Milan-X represents a unique product in the x86 market, offering so much L3 cache on each chip that you can imagine AMD could offer a better premium than a regular Milan.
We are told it will be launched in the first three months of next year (q1 2022). However, AMD is keen to point out that the increased cache reduces the bandwidth pressure on main memory, allowing for a 66% improvement in the speed of some workloads (for EDA-BASED RTL validation on Synopsys VCS) when comparing a 16-core Milan to a 16-core Milan-X, although the exact chip configuration is not public.
AMD also said Microsoft will release a public preview of its Azure HBV3 series of virtual machines at Milan-X today, but did not discuss availability. In addition, one would normally expect major OEM partners (Dell, Lenovo, HP, AMD, and Cisco) to adopt new hardware for a full release.
